Passive element memory arrays, such as anti-fuse diode cell arrays, require a high-voltage and high-current programming voltage source due to the large number of leakage paths in the array and the high voltage required to program the element conductivity. The write power dissipation is dominated by the power of the programming voltage source, and the write power increases the temperature of the memory. As the temperature of the diodes increases, the diode leakage current and the write power further increase, and this feedback can cause thermal run-away and failure of the memory. While large sub-arrays are more efficient in area because support circuits are shared by more memory cells, large sub-arrays are usually associated with high leakage current. For example, in high-density anti-fuse diode memory arrays with contiguous memory cell sub-arrays of N-by-N cells stacked in multiple layers, the leakage current increases by N2 as N increases. To reduce the chance of thermal run-away, the memory array can be subdivided into smaller sub-arrays to decrease the number of memory cells that are simultaneously accessed. However, this design can increase the cost per unit of storage capacity and can result in a relatively slow memory device.
There is a need, therefore, for a memory device and method that will avoid thermal run-away while maintaining a relatively low cost and high data rate.